https://circuitdiagram.net/nand-gate-clock-generator.html Schematic & PCB Design Sat, 01 Jun 2019 22:34:44 +0000 hourly 1 https://circuitdiagram.net/nand-gate-clock-generator.html#comment-323485 Sat, 01 Jun 2019 22:34:44 +0000 http://circuitdiagram.net/?p=757#comment-323485 Better to use a Schmitt trigger IC to do this. 7414 etc

]]> https://circuitdiagram.net/nand-gate-clock-generator.html#comment-314492 Thu, 29 Nov 2018 01:00:50 +0000 http://circuitdiagram.net/?p=757#comment-314492 2018.11.28
I tried to repro this circuit with an [SN 74 LS 00 N, by Texas Instruments], but even with a 47uF and 5MOhm resistor, the frequency seems to be around 175MHz to 200MHz (which is purely estimated since by scope is officially limited to only 100 MHz) AND the signal voltage and is sinusoidal and is always under 2.0V (doesn’t trigger even a little bit below that) which is the logic level for a High accordingly to the datasheet. The cap is electrolytic, but the same behavior seems to be repeated for a film cap (1uF though) or for ceramic caps. Is there a counter indication about this circuit for the LS category of the 7400 chips? My wiring seems ok (on a breadboard), being able to trigger the right outputs accordingly to the proper inputs. I know that there are other possible circuits out there, but I am particularly interested by this one only, and wish to know it I have to forget it completely, or if there is a “fix” or if someone is with an idea to keep the basic idea of this circuit.

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